This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Liberty (.lib) files gather data used by electronic design automation (EDA) tools to perform static timing analysis (STA) and power analysis of circuit blocks. Typically, for each variation in parameters settings, a liberty (.lib) file is generated. Unfortunately, this process can use significant amounts of computing resources and time.
Conventionally, to model timing of a multi-bit bus, timing for each bit of the bus is characterized, and a worst case timing model of the whole bus is reported in a liberty file. With advanced technology nodes, conventional methods introduce unnecessary and unacceptable pessimism in timing models. Some conventional methods report the timing model for each bit of the bus. This method introduces problems by dramatically increasing complexity, timing-database size and liberty model size, and by significantly increasing cost of model generation and verification. Also, these conventional methods do not apply to memory compiler. For instance, if timing is modeled for each bit of the bus, it can be difficult to determine which data should be used for calculation because some memory instances can have a different number of bits than characterized instances.